1. Field of the Invention
The present invention relates to a read-only nonvolatile memory such as a mask ROM (Read Only Memory).
2. Description of Related Art
A mask ROM is a known example of a read-only nonvolatile memory.
A mask ROM comprises memory cell transistors laid out in a matrix, and binary data is written to each memory cell transistor at the manufacturing stage. This binary data is written as the level of the operating threshold of each memory cell transistor. The operating threshold of a transistor can be controlled, for example, by varying the impurity concentration of a channel formation region. In the following description, the stored value will be xe2x80x9c1xe2x80x9d when the operating threshold is low, and will be xe2x80x9c0xe2x80x9d when the operating threshold is high.
In each memory cell transistor, a gate is connected to a word line, the source is connected to a source line, and the drain is connected to a drain line.
When the potential difference between a source line and a drain line is suitably set and the word line is activated, a memory cell transistor with a low operating threshold is switched on, while a memory cell transistor with a high operating threshold is not. Therefore, the level of the operating threshold, that is, the value of the written binary data, can be determined from the value of the current that flows out to the source lines.
A small amount of current may be leaked at a memory cell transistor although the transistor is off. Leakage current is more apt to occur at a transistor with a low operating threshold. Therefore, when data is being read out from a memory cell transistor with a high operating threshold, leakage current may flow from a memory cell transistor with a low operating threshold to a source line. In this case, a small amount of current will flow to the source line even though the current value corresponding to the read data is zero. This phenomenon reduces the read margin of a memory cell transistor. Leakage current flows when a potential difference is generated between the source and drain of a memory cell transistor that is off. This potential difference can be caused by an increase in the potential of another source line, or by a charge accumulated in the parasitic capacitance of another source line or drain line. The accumulated charge of parasitic capacitance can be eliminated by discharging, but this discharging lowers the substantial operating speed of a mask ROM.
When the integration is increased or the power consumption lowered for a read-only nonvolatile memory, it is necessary to lower the current value when a memory cell transistor is on. The lower the ON current is set for a memory cell transistor, the greater the effect of leakage current. Also, increasingly higher operating speeds are being required of read-only nonvolatile memories.
It is an object of the present invention to provide a read-only nonvolatile memory with a large read margin and a high operating speed.
To this end, the read-only nonvolatile memory pertaining to the present invention comprises a plurality of memory cell transistors, disposed in a matrix, and disposed such that source diffusion regions and drain diffusion regions are respectively opposing to each other within the same row, a plurality of row selection lines commonly connected to the gate electrodes of the memory cell transistors belonging to the same row, a plurality of drain lines each commonly connected to two opposing columns of the drain diffusion regions, a plurality of source lines each commonly connected to two opposing columns of the source diffusion regions, an offset structure formed between the gate electrode and said drain diffusion region of each memory cell transistor, and a non-offset structure formed between the gate electrode and said source diffusion region of each memory cell transistor.
With the constitution of the present invention, it is possible to prevent the flow of current from a memory cell transistor that has been set to OFF to a source line.
In the present invention, xe2x80x9coffset structurexe2x80x9d refers to a structure in which the depletion layer directly under a diffusion region extends to the channel when a specific voltage has been applied to that diffusion region, but in which the depletion layer directly under that diffusion region does not extend to the channel when the diffusion region is in a state of high impedance.